--- drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h.orig	2018-05-13 11:55:14.140000000 +0200
+++ drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h	2018-05-13 11:55:29.148000000 +0200
@@ -69,7 +69,6 @@
 #define UCODE_FLAG_UNHALT_MASK   0x1
 
 struct SMU_Entry {
-#ifndef __BIG_ENDIAN
 	uint16_t id;
 	uint16_t version;
 	uint32_t image_addr_high;
@@ -79,17 +78,6 @@
 	uint32_t data_size_byte;
 	uint16_t flags;
 	uint16_t num_register_entries;
-#else
-	uint16_t version;
-	uint16_t id;
-	uint32_t image_addr_high;
-	uint32_t image_addr_low;
-	uint32_t meta_data_addr_high;
-	uint32_t meta_data_addr_low;
-	uint32_t data_size_byte;
-	uint16_t num_register_entries;
-	uint16_t flags;
-#endif
 };
 
 struct SMU_DRAMData_TOC {
--- drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c.orig	2018-05-13 14:36:30.668000000 +0200
+++ drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c	2018-05-15 19:40:20.704000000 +0200
@@ -183,10 +183,10 @@
 					ATOM_Tonga_Voltage_Lookup_Record,
 					entries, vddc_lookup_pp_tables, i);
 		record->us_calculated = 0;
-		record->us_vdd = atom_record->usVdd;
-		record->us_cac_low = atom_record->usCACLow;
-		record->us_cac_mid = atom_record->usCACMid;
-		record->us_cac_high = atom_record->usCACHigh;
+		record->us_vdd = le16_to_cpu(atom_record->usVdd);
+		record->us_cac_low = le16_to_cpu(atom_record->usCACLow);
+		record->us_cac_mid = le16_to_cpu(atom_record->usCACMid);
+		record->us_cac_high = le16_to_cpu(atom_record->usCACHigh);
 	}
 
 	*lookup_table = table;
@@ -214,23 +214,23 @@
 	ptr->ppm_design
 		= atom_ppm_table->ucPpmDesign;
 	ptr->cpu_core_number
-		= atom_ppm_table->usCpuCoreNumber;
+		= le16_to_cpu(atom_ppm_table->usCpuCoreNumber);
 	ptr->platform_tdp
-		= atom_ppm_table->ulPlatformTDP;
+		= le32_to_cpu(atom_ppm_table->ulPlatformTDP);
 	ptr->small_ac_platform_tdp
-		= atom_ppm_table->ulSmallACPlatformTDP;
+		= le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDP);
 	ptr->platform_tdc
-		= atom_ppm_table->ulPlatformTDC;
+		= le32_to_cpu(atom_ppm_table->ulPlatformTDC);
 	ptr->small_ac_platform_tdc
-		= atom_ppm_table->ulSmallACPlatformTDC;
+		= le32_to_cpu(atom_ppm_table->ulSmallACPlatformTDC);
 	ptr->apu_tdp
-		= atom_ppm_table->ulApuTDP;
+		= le32_to_cpu(atom_ppm_table->ulApuTDP);
 	ptr->dgpu_tdp
-		= atom_ppm_table->ulDGpuTDP;
+		= le32_to_cpu(atom_ppm_table->ulDGpuTDP);
 	ptr->dgpu_ulv_power
-		= atom_ppm_table->ulDGpuUlvPower;
+		= le32_to_cpu(atom_ppm_table->ulDGpuUlvPower);
 	ptr->tj_max
-		= atom_ppm_table->ulTjmax;
+		= le32_to_cpu(atom_ppm_table->ulTjmax);
 
 	pp_table_information->ppm_parameter_table = ptr;
 
@@ -396,10 +396,10 @@
 					ATOM_Tonga_MCLK_Dependency_Record,
 						entries, mclk_dep_table, i);
 		mclk_table_record->vddInd = mclk_dep_record->ucVddcInd;
-		mclk_table_record->vdd_offset = mclk_dep_record->usVddgfxOffset;
-		mclk_table_record->vddci = mclk_dep_record->usVddci;
-		mclk_table_record->mvdd = mclk_dep_record->usMvdd;
-		mclk_table_record->clk = mclk_dep_record->ulMclk;
+		mclk_table_record->vdd_offset = le16_to_cpu(mclk_dep_record->usVddgfxOffset);
+		mclk_table_record->vddci = le16_to_cpu(mclk_dep_record->usVddci);
+		mclk_table_record->mvdd = le16_to_cpu(mclk_dep_record->usMvdd);
+		mclk_table_record->clk = le32_to_cpu(mclk_dep_record->ulMclk);
 	}
 
 	*pp_tonga_mclk_dep_table = mclk_table;
@@ -443,8 +443,8 @@
 						phm_ppt_v1_clock_voltage_dependency_record,
 						entries, sclk_table, i);
 			sclk_table_record->vddInd = sclk_dep_record->ucVddInd;
-			sclk_table_record->vdd_offset = sclk_dep_record->usVddcOffset;
-			sclk_table_record->clk = sclk_dep_record->ulSclk;
+			sclk_table_record->vdd_offset = le16_to_cpu(sclk_dep_record->usVddcOffset);
+			sclk_table_record->clk = le32_to_cpu(sclk_dep_record->ulSclk);
 			sclk_table_record->cks_enable =
 				(((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
 			sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F);
@@ -475,12 +475,13 @@
 						phm_ppt_v1_clock_voltage_dependency_record,
 						entries, sclk_table, i);
 			sclk_table_record->vddInd = sclk_dep_record->ucVddInd;
-			sclk_table_record->vdd_offset = sclk_dep_record->usVddcOffset;
-			sclk_table_record->clk = sclk_dep_record->ulSclk;
+			sclk_table_record->vdd_offset = le16_to_cpu(sclk_dep_record->usVddcOffset);
+			sclk_table_record->clk = le32_to_cpu(sclk_dep_record->ulSclk);
 			sclk_table_record->cks_enable =
 				(((sclk_dep_record->ucCKSVOffsetandDisable & 0x80) >> 7) == 0) ? 1 : 0;
 			sclk_table_record->cks_voffset = (sclk_dep_record->ucCKSVOffsetandDisable & 0x7F);
-			sclk_table_record->sclk_offset = sclk_dep_record->ulSclkOffset;
+			sclk_table_record->sclk_offset = le32_to_cpu(sclk_dep_record->ulSclkOffset);
+			printk("polaris_table[%u].clk = 0x%08x\n", (unsigned)i, (unsigned)sclk_table_record->clk);
 		}
 	}
 	*pp_tonga_sclk_dep_table = sclk_table;
@@ -577,7 +578,7 @@
 						entries, atom_pcie_table, i);
 			pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed;
 			pcie_record->lane_width = atom_pcie_record->usPCIELaneWidth;
-			pcie_record->pcie_sclk = atom_pcie_record->ulPCIE_Sclk;
+			pcie_record->pcie_sclk = le32_to_cpu(atom_pcie_record->ulPCIE_Sclk);
 		}
 
 		*pp_tonga_pcie_table = pcie_table;
@@ -611,64 +612,64 @@
 	if (table->ucRevId < 3) {
 		const ATOM_Tonga_PowerTune_Table *tonga_table =
 			(ATOM_Tonga_PowerTune_Table *)table;
-		tdp_table->usTDP = tonga_table->usTDP;
+		tdp_table->usTDP = le16_to_cpu(tonga_table->usTDP);
 		tdp_table->usConfigurableTDP =
-			tonga_table->usConfigurableTDP;
-		tdp_table->usTDC = tonga_table->usTDC;
+			le16_to_cpu(tonga_table->usConfigurableTDP);
+		tdp_table->usTDC = le16_to_cpu(tonga_table->usTDC);
 		tdp_table->usBatteryPowerLimit =
-			tonga_table->usBatteryPowerLimit;
+			le16_to_cpu(tonga_table->usBatteryPowerLimit);
 		tdp_table->usSmallPowerLimit =
-			tonga_table->usSmallPowerLimit;
+			le16_to_cpu(tonga_table->usSmallPowerLimit);
 		tdp_table->usLowCACLeakage =
-			tonga_table->usLowCACLeakage;
+			le16_to_cpu(tonga_table->usLowCACLeakage);
 		tdp_table->usHighCACLeakage =
-			tonga_table->usHighCACLeakage;
+			le16_to_cpu(tonga_table->usHighCACLeakage);
 		tdp_table->usMaximumPowerDeliveryLimit =
-			tonga_table->usMaximumPowerDeliveryLimit;
+			le16_to_cpu(tonga_table->usMaximumPowerDeliveryLimit);
 		tdp_table->usDefaultTargetOperatingTemp =
-			tonga_table->usTjMax;
+			le16_to_cpu(tonga_table->usTjMax);
 		tdp_table->usTargetOperatingTemp =
-			tonga_table->usTjMax; /*Set the initial temp to the same as default */
+			le16_to_cpu(tonga_table->usTjMax); /*Set the initial temp to the same as default */
 		tdp_table->usPowerTuneDataSetID =
-			tonga_table->usPowerTuneDataSetID;
+			le16_to_cpu(tonga_table->usPowerTuneDataSetID);
 		tdp_table->usSoftwareShutdownTemp =
-			tonga_table->usSoftwareShutdownTemp;
+			le16_to_cpu(tonga_table->usSoftwareShutdownTemp);
 		tdp_table->usClockStretchAmount =
-			tonga_table->usClockStretchAmount;
+			le16_to_cpu(tonga_table->usClockStretchAmount);
 	} else {   /* Fiji and newer */
 		const ATOM_Fiji_PowerTune_Table *fijitable =
 			(ATOM_Fiji_PowerTune_Table *)table;
-		tdp_table->usTDP = fijitable->usTDP;
-		tdp_table->usConfigurableTDP = fijitable->usConfigurableTDP;
-		tdp_table->usTDC = fijitable->usTDC;
-		tdp_table->usBatteryPowerLimit = fijitable->usBatteryPowerLimit;
-		tdp_table->usSmallPowerLimit = fijitable->usSmallPowerLimit;
-		tdp_table->usLowCACLeakage = fijitable->usLowCACLeakage;
-		tdp_table->usHighCACLeakage = fijitable->usHighCACLeakage;
+		tdp_table->usTDP = le16_to_cpu(fijitable->usTDP);
+		tdp_table->usConfigurableTDP = le16_to_cpu(fijitable->usConfigurableTDP);
+		tdp_table->usTDC = le16_to_cpu(fijitable->usTDC);
+		tdp_table->usBatteryPowerLimit = le16_to_cpu(fijitable->usBatteryPowerLimit);
+		tdp_table->usSmallPowerLimit = le16_to_cpu(fijitable->usSmallPowerLimit);
+		tdp_table->usLowCACLeakage = le16_to_cpu(fijitable->usLowCACLeakage);
+		tdp_table->usHighCACLeakage = le16_to_cpu(fijitable->usHighCACLeakage);
 		tdp_table->usMaximumPowerDeliveryLimit =
-			fijitable->usMaximumPowerDeliveryLimit;
+			le16_to_cpu(fijitable->usMaximumPowerDeliveryLimit);
 		tdp_table->usDefaultTargetOperatingTemp =
-			fijitable->usTjMax;
+			le16_to_cpu(fijitable->usTjMax);
 		tdp_table->usTargetOperatingTemp =
-			fijitable->usTjMax; /*Set the initial temp to the same as default */
+			le16_to_cpu(fijitable->usTjMax); /*Set the initial temp to the same as default */
 		tdp_table->usPowerTuneDataSetID =
-			fijitable->usPowerTuneDataSetID;
+			le16_to_cpu(fijitable->usPowerTuneDataSetID);
 		tdp_table->usSoftwareShutdownTemp =
-			fijitable->usSoftwareShutdownTemp;
+			le16_to_cpu(fijitable->usSoftwareShutdownTemp);
 		tdp_table->usClockStretchAmount =
-			fijitable->usClockStretchAmount;
+			le16_to_cpu(fijitable->usClockStretchAmount);
 		tdp_table->usTemperatureLimitHotspot =
-			fijitable->usTemperatureLimitHotspot;
+			le16_to_cpu(fijitable->usTemperatureLimitHotspot);
 		tdp_table->usTemperatureLimitLiquid1 =
-			fijitable->usTemperatureLimitLiquid1;
+			le16_to_cpu(fijitable->usTemperatureLimitLiquid1);
 		tdp_table->usTemperatureLimitLiquid2 =
-			fijitable->usTemperatureLimitLiquid2;
+			le16_to_cpu(fijitable->usTemperatureLimitLiquid2);
 		tdp_table->usTemperatureLimitVrVddc =
-			fijitable->usTemperatureLimitVrVddc;
+			le16_to_cpu(fijitable->usTemperatureLimitVrVddc);
 		tdp_table->usTemperatureLimitVrMvdd =
-			fijitable->usTemperatureLimitVrMvdd;
+			le16_to_cpu(fijitable->usTemperatureLimitVrMvdd);
 		tdp_table->usTemperatureLimitPlx =
-			fijitable->usTemperatureLimitPlx;
+			le16_to_cpu(fijitable->usTemperatureLimitPlx);
 		tdp_table->ucLiquid1_I2C_address =
 			fijitable->ucLiquid1_I2C_address;
 		tdp_table->ucLiquid2_I2C_address =
@@ -717,12 +718,12 @@
 					phm_ppt_v1_mm_clock_voltage_dependency_record,
 					entries, mm_table, i);
 		mm_table_record->vddcInd = mm_dependency_record->ucVddcInd;
-		mm_table_record->vddgfx_offset = mm_dependency_record->usVddgfxOffset;
-		mm_table_record->aclk = mm_dependency_record->ulAClk;
-		mm_table_record->samclock = mm_dependency_record->ulSAMUClk;
-		mm_table_record->eclk = mm_dependency_record->ulEClk;
-		mm_table_record->vclk = mm_dependency_record->ulVClk;
-		mm_table_record->dclk = mm_dependency_record->ulDClk;
+		mm_table_record->vddgfx_offset = le16_to_cpu(mm_dependency_record->usVddgfxOffset);
+		mm_table_record->aclk = le32_to_cpu(mm_dependency_record->ulAClk);
+		mm_table_record->samclock = le32_to_cpu(mm_dependency_record->ulSAMUClk);
+		mm_table_record->eclk = le32_to_cpu(mm_dependency_record->ulEClk);
+		mm_table_record->vclk = le32_to_cpu(mm_dependency_record->ulVClk);
+		mm_table_record->dclk = le32_to_cpu(mm_dependency_record->ulDClk);
 	}
 
 	*tonga_mm_table = mm_table;
@@ -913,33 +914,33 @@
 		hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
 			= tonga_fan_table->ucTHyst;
 		hwmgr->thermal_controller.advanceFanControlParameters.usTMin
-			= tonga_fan_table->usTMin;
+			= le16_to_cpu(tonga_fan_table->usTMin);
 		hwmgr->thermal_controller.advanceFanControlParameters.usTMed
-			= tonga_fan_table->usTMed;
+			= le16_to_cpu(tonga_fan_table->usTMed);
 		hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
-			= tonga_fan_table->usTHigh;
+			= le16_to_cpu(tonga_fan_table->usTHigh);
 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
-			= tonga_fan_table->usPWMMin;
+			= le16_to_cpu(tonga_fan_table->usPWMMin);
 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
-			= tonga_fan_table->usPWMMed;
+			= le16_to_cpu(tonga_fan_table->usPWMMed);
 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
-			= tonga_fan_table->usPWMHigh;
+			= le16_to_cpu(tonga_fan_table->usPWMHigh);
 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
 			= 10900;                  /* hard coded */
 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
-			= tonga_fan_table->usTMax;
+			= le16_to_cpu(tonga_fan_table->usTMax);
 		hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
 			= tonga_fan_table->ucFanControlMode;
 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
-			= tonga_fan_table->usFanPWMMax;
+			= le16_to_cpu(tonga_fan_table->usFanPWMMax);
 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
 			= 4836;
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
-			= tonga_fan_table->usFanOutputSensitivity;
+			= le16_to_cpu(tonga_fan_table->usFanOutputSensitivity);
 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
-			= tonga_fan_table->usFanRPMMax;
+			= le16_to_cpu(tonga_fan_table->usFanRPMMax);
 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
-			= (tonga_fan_table->ulMinFanSCLKAcousticLimit / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
+			= (le32_to_cpu(tonga_fan_table->ulMinFanSCLKAcousticLimit) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
 		hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
 			= tonga_fan_table->ucTargetTemperature;
 		hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
@@ -950,50 +951,50 @@
 		hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
 			= fiji_fan_table->ucTHyst;
 		hwmgr->thermal_controller.advanceFanControlParameters.usTMin
-			= fiji_fan_table->usTMin;
+			= le16_to_cpu(fiji_fan_table->usTMin);
 		hwmgr->thermal_controller.advanceFanControlParameters.usTMed
-			= fiji_fan_table->usTMed;
+			= le16_to_cpu(fiji_fan_table->usTMed);
 		hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
-			= fiji_fan_table->usTHigh;
+			= le16_to_cpu(fiji_fan_table->usTHigh);
 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
-			= fiji_fan_table->usPWMMin;
+			= le16_to_cpu(fiji_fan_table->usPWMMin);
 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
-			= fiji_fan_table->usPWMMed;
+			= le16_to_cpu(fiji_fan_table->usPWMMed);
 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
-			= fiji_fan_table->usPWMHigh;
+			= le16_to_cpu(fiji_fan_table->usPWMHigh);
 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
-			= fiji_fan_table->usTMax;
+			= le16_to_cpu(fiji_fan_table->usTMax);
 		hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
 			= fiji_fan_table->ucFanControlMode;
 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
-			= fiji_fan_table->usFanPWMMax;
+			= le16_to_cpu(fiji_fan_table->usFanPWMMax);
 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
 			= 4836;
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
-			= fiji_fan_table->usFanOutputSensitivity;
+			= le16_to_cpu(fiji_fan_table->usFanOutputSensitivity);
 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
-			= fiji_fan_table->usFanRPMMax;
+			= le16_to_cpu(fiji_fan_table->usFanRPMMax);
 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
-			= (fiji_fan_table->ulMinFanSCLKAcousticLimit / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
+			= (le32_to_cpu(fiji_fan_table->ulMinFanSCLKAcousticLimit) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
 		hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
 			= fiji_fan_table->ucTargetTemperature;
 		hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
 			= fiji_fan_table->ucMinimumPWMLimit;
 
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge
-			= fiji_fan_table->usFanGainEdge;
+			= le16_to_cpu(fiji_fan_table->usFanGainEdge);
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot
-			= fiji_fan_table->usFanGainHotspot;
+			= le16_to_cpu(fiji_fan_table->usFanGainHotspot);
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid
-			= fiji_fan_table->usFanGainLiquid;
+			= le16_to_cpu(fiji_fan_table->usFanGainLiquid);
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc
-			= fiji_fan_table->usFanGainVrVddc;
+			= le16_to_cpu(fiji_fan_table->usFanGainVrVddc);
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd
-			= fiji_fan_table->usFanGainVrMvdd;
+			= le16_to_cpu(fiji_fan_table->usFanGainVrMvdd);
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx
-			= fiji_fan_table->usFanGainPlx;
+			= le16_to_cpu(fiji_fan_table->usFanGainPlx);
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm
-			= fiji_fan_table->usFanGainHbm;
+			= le16_to_cpu(fiji_fan_table->usFanGainHbm);
 	}
 
 	return 0;
@@ -1227,9 +1228,9 @@
 					vce_state_record->ucVCEClockIndex);
 	*flag = vce_state_record->ucFlag;
 
-	vce_state->evclk = mm_dep_record->ulEClk;
-	vce_state->ecclk = mm_dep_record->ulEClk;
-	vce_state->sclk = sclk_dep_record->ulSclk;
+	vce_state->evclk = le32_to_cpu(mm_dep_record->ulEClk);
+	vce_state->ecclk = le32_to_cpu(mm_dep_record->ulEClk);
+	vce_state->sclk = le32_to_cpu(sclk_dep_record->ulSclk);
 
 	if (vce_state_record->ucMCLKIndex >= mclk_dep_table->ucNumEntries)
 		mclk_dep_record = GET_FLEXIBLE_ARRAY_MEMBER_ADDR(
@@ -1242,7 +1243,7 @@
 					entries, mclk_dep_table,
 					vce_state_record->ucMCLKIndex);
 
-	vce_state->mclk = mclk_dep_record->ulMclk;
+	vce_state->mclk = le32_to_cpu(mclk_dep_record->ulMclk);
 	return 0;
 }
 
--- drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c.orig	2018-05-13 22:50:16.256000000 +0200
+++ drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c	2018-05-14 13:02:05.440000000 +0200
@@ -43,6 +43,26 @@
 	struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
 };
 
+static void atomctrl_swap_lbf(void *bf, bool to_le)
+{
+#ifdef __BIG_ENDIAN
+	uint32_t tmp;
+
+	if (to_le) {
+		memcpy(&tmp, bf, sizeof(uint32_t));
+		tmp = cpu_to_le32(tmp);
+		memcpy(bf, &tmp, sizeof(uint32_t));
+	} else {
+		memcpy(&tmp, bf, sizeof(uint32_t));
+		tmp = le32_to_cpu(tmp);
+		memcpy(bf, &tmp, sizeof(uint32_t));
+	}
+#else
+	(void)bf;
+	(void)to_le;
+#endif
+}
+
 static int atomctrl_retrieve_ac_timing(
 		uint8_t index,
 		ATOM_INIT_REG_BLOCK *reg_block,
@@ -57,18 +77,18 @@
 
 	while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK &&
 			num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES) {
-		tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
+		tmem_id = (uint8_t)((le32_to_cpu(*(uint32_t *)reg_data) & MEM_ID_MASK) >> MEM_ID_SHIFT);
 
 		if (index == tmem_id) {
 			table->mc_reg_table_entry[num_ranges].mclk_max =
-				(uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >>
+				(uint32_t)((le32_to_cpu(*(uint32_t *)reg_data) & CLOCK_RANGE_MASK) >>
 						CLOCK_RANGE_SHIFT);
 
 			for (i = 0, j = 1; i < table->last; i++) {
 				if ((table->mc_reg_address[i].uc_pre_reg_data &
 							LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
 					table->mc_reg_table_entry[num_ranges].mc_data[i] =
-						(uint32_t)*((uint32_t *)reg_data + j);
+						(uint32_t)le32_to_cpu(*((uint32_t *)reg_data + j));
 					j++;
 				} else if ((table->mc_reg_address[i].uc_pre_reg_data &
 							LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
@@ -298,15 +318,18 @@
 	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;
 	int result;
 
-	mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
+	mpll_parameters.ulClock.ulClock = clock_value;
+	atomctrl_swap_lbf(&mpll_parameters.ulClock, 1);
 
 	result = cgs_atom_exec_cmd_table(hwmgr->device,
 			GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
 			&mpll_parameters);
 
-	if (!result)
+	if (!result) {
+		atomctrl_swap_lbf(&mpll_parameters.ulClock, 0);
 		mpll_param->mpll_post_divider =
 				(uint32_t)mpll_parameters.ulClock.ucPostDiv;
+	}
 
 	return result;
 }
@@ -318,7 +341,8 @@
 	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
 	int result;
 
-	pll_parameters.ulClock = cpu_to_le32(clock_value);
+	pll_parameters.ulClock = clock_value;
+	atomctrl_swap_lbf(&pll_parameters, 1);
 
 	result = cgs_atom_exec_cmd_table
 		(hwmgr->device,
@@ -326,8 +350,9 @@
 		 &pll_parameters);
 
 	if (0 == result) {
+		atomctrl_swap_lbf(&pll_parameters, 0);
 		dividers->pll_post_divider = pll_parameters.ucPostDiv;
-		dividers->real_clock = le32_to_cpu(pll_parameters.ulClock);
+		dividers->real_clock = pll_parameters.ulClock;
 	}
 
 	return result;
@@ -341,8 +366,9 @@
 	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
 	int result;
 
-	pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
+	pll_patameters.ulClock.ulClock = clock_value;
 	pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
+	atomctrl_swap_lbf(&pll_patameters.ulClock, 1);
 
 	result = cgs_atom_exec_cmd_table
 		(hwmgr->device,
@@ -350,10 +376,11 @@
 		 &pll_patameters);
 
 	if (0 == result) {
+		atomctrl_swap_lbf(&pll_patameters.ulClock, 0);
 		dividers->pll_post_divider =
 			pll_patameters.ulClock.ucPostDiv;
 		dividers->real_clock =
-			le32_to_cpu(pll_patameters.ulClock.ulClock);
+			pll_patameters.ulClock.ulClock;
 
 		dividers->ul_fb_div.ul_fb_div_frac =
 			le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac);
@@ -378,8 +405,9 @@
 	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;
 	int result;
 
-	pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
+	pll_patameters.ulClock.ulClock = clock_value;
 	pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
+	atomctrl_swap_lbf(&pll_patameters.ulClock, 1);
 
 	result = cgs_atom_exec_cmd_table
 		(hwmgr->device,
@@ -410,9 +438,10 @@
 	COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
 	int result;
 
-	pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
+	pll_patameters.ulClock.ulClock = clock_value;
 	pll_patameters.ulClock.ucPostDiv =
 		COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK;
+	atomctrl_swap_lbf(&pll_patameters.ulClock, 1);
 
 	result = cgs_atom_exec_cmd_table
 		(hwmgr->device,
@@ -420,10 +449,11 @@
 		 &pll_patameters);
 
 	if (0 == result) {
+		atomctrl_swap_lbf(&pll_patameters.ulClock, 0);
 		dividers->pll_post_divider =
 			pll_patameters.ulClock.ucPostDiv;
 		dividers->real_clock =
-			le32_to_cpu(pll_patameters.ulClock.ulClock);
+			pll_patameters.ulClock.ulClock;
 
 		dividers->ul_fb_div.ul_fb_div_frac =
 			le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac);
@@ -656,7 +686,7 @@
 	 *GETTING MULTI-STEP PARAMETERS RELATED TO CURRENT DPM LEVEL
 	 *-----------------------------------------------------------
 	 */
-	fRLL_LoadLine = Divide(getASICProfilingInfo->ulLoadLineSlop, 1000);
+	fRLL_LoadLine = Divide(le32_to_cpu(getASICProfilingInfo->ulLoadLineSlop), 1000);
 
 	switch (dpm_level) {
 	case 1:
@@ -1107,7 +1137,7 @@
 
 	get_voltage_info_param_space.ucVoltageType = VOLTAGE_TYPE_VDDC;
 	get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
-	get_voltage_info_param_space.usVoltageLevel = virtual_voltage_id;
+	get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
 	get_voltage_info_param_space.ulSCLKFreq =
 		cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);
 
@@ -1291,6 +1321,7 @@
 		memory_clock & SET_CLOCK_FREQ_MASK;
 	memory_clock_parameters.asDPMMCReg.ulClock.ulComputeClockFlag =
 		ADJUST_MC_SETTING_PARAM;
+	atomctrl_swap_lbf(&memory_clock_parameters.asDPMMCReg.ulClock, 1);
 	memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;
 
 	result = cgs_atom_exec_cmd_table
@@ -1414,7 +1445,7 @@
 
 	*svd_gpio_id = voltage_object->asSVID2Obj.ucSVDGpioId;
 	*svc_gpio_id = voltage_object->asSVID2Obj.ucSVCGpioId;
-	*load_line = voltage_object->asSVID2Obj.usLoadLine_PSI;
+	*load_line = le16_to_cpu(voltage_object->asSVID2Obj.usLoadLine_PSI);
 
 	return 0;
 }
@@ -1432,7 +1463,7 @@
 			GetIndexIntoMasterTable(COMMAND, SetVoltage),
 			voltage_parameters);
 
-	*virtual_voltage_id = voltage_parameters->usVoltageLevel;
+	*virtual_voltage_id = le16_to_cpu(voltage_parameters->usVoltageLevel);
 
 	return result;
 }
@@ -1461,10 +1492,10 @@
 
 	if ((profile->asHeader.ucTableFormatRevision >= 2) &&
 		(profile->asHeader.ucTableContentRevision >= 1) &&
-		(profile->asHeader.usStructureSize >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) {
-		leakage_bin = (u16 *)((char *)profile + profile->usLeakageBinArrayOffset);
-		vddc_id_buf = (u16 *)((char *)profile + profile->usElbVDDC_IdArrayOffset);
-		vddc_buf = (u16 *)((char *)profile + profile->usElbVDDC_LevelArrayOffset);
+		(le16_to_cpu(profile->asHeader.usStructureSize) >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) {
+		leakage_bin = (u16 *)((char *)profile + le16_to_cpu(profile->usLeakageBinArrayOffset));
+		vddc_id_buf = (u16 *)((char *)profile + le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
+		vddc_buf = (u16 *)((char *)profile + le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
 		if (profile->ucElbVDDC_Num > 0) {
 			for (i = 0; i < profile->ucElbVDDC_Num; i++) {
 				if (vddc_id_buf[i] == virtual_voltage_id) {
@@ -1479,8 +1510,8 @@
 			}
 		}
 
-		vddci_id_buf = (u16 *)((char *)profile + profile->usElbVDDCI_IdArrayOffset);
-		vddci_buf   = (u16 *)((char *)profile + profile->usElbVDDCI_LevelArrayOffset);
+		vddci_id_buf = (u16 *)((char *)profile + le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
+		vddci_buf   = (u16 *)((char *)profile + le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
 		if (profile->ucElbVDDCI_Num > 0) {
 			for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
 				if (vddci_id_buf[i] == virtual_voltage_id) {
--- drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c.orig	2018-05-11 23:36:48.340000000 +0200
+++ drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c	2018-06-12 15:00:51.188000000 +0200
@@ -394,7 +394,7 @@
 {
 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 	uint32_t fw_to_load;
-	int result = 0;
+	int i, result = 0;
 	struct SMU_DRAMData_TOC *toc;
 
 	if (!hwmgr->reload_fw) {
@@ -472,6 +472,20 @@
 				UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
 				"Failed to Get Firmware Entry.", return -EINVAL);
 
+	for (i = 0; i < toc->num_entries; i++) {
+		toc->entry[i].id = cpu_to_le16(toc->entry[i].id);
+		toc->entry[i].version = cpu_to_le16(toc->entry[i].version);
+		toc->entry[i].image_addr_high = cpu_to_le32(toc->entry[i].image_addr_high);
+		toc->entry[i].image_addr_low = cpu_to_le32(toc->entry[i].image_addr_low);
+		toc->entry[i].meta_data_addr_high = cpu_to_le32(toc->entry[i].meta_data_addr_high);
+		toc->entry[i].meta_data_addr_low = cpu_to_le32(toc->entry[i].meta_data_addr_low);
+		toc->entry[i].data_size_byte = cpu_to_le32(toc->entry[i].data_size_byte);
+		toc->entry[i].flags = cpu_to_le16(toc->entry[i].flags);
+		toc->entry[i].num_register_entries = cpu_to_le16(toc->entry[i].num_register_entries);
+	}
+	toc->structure_version = cpu_to_le32(toc->structure_version);
+	toc->num_entries = cpu_to_le32(toc->num_entries);
+
 	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
 	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
 
@@ -500,17 +514,21 @@
 	return hwmgr->smumgr_funcs->start_smu(hwmgr);
 }
 
-static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
+static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint8_t *src, uint32_t limit)
 {
 	uint32_t byte_count = length;
+	uint32_t data;
 
 	PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
 
 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);
 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
 
-	for (; byte_count >= 4; byte_count -= 4)
-		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);
+	for (; byte_count >= 4; byte_count -= 4) {
+		data = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
+		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
+		src += 4;
+	}
 
 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
 
@@ -536,7 +554,7 @@
 
 	hwmgr->is_kicker = info.is_kicker;
 
-	result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
+	result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint8_t *)info.kptr, SMU7_SMC_SIZE);
 
 	return result;
 }
--- drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c.orig	2018-05-12 17:11:49.392000000 +0200
+++ drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c	2018-06-12 15:04:23.684000000 +0200
@@ -78,6 +78,8 @@
 
 #define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
 
+#ifdef __LITTLE_ENDIAN
+
 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
 	/*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
 	/* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
@@ -94,6 +96,26 @@
 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
 	0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
 
+#else
+
+static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
+	/*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
+	/* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
+	{ 0x46a40e10, 0x00, 0x03, 0x32, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x07530, 0x30, 0, 0x26, 0, 0, 0x400, 0x28f, 0xffff, 0x2f, 0x0e30, 0x27 } },
+	{ 0x46a40e40, 0x01, 0x04, 0x32, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x09c40, 0x20, 0, 0x1e, 1, 1, 0x400, 0x083, 0xffff, 0x1f, 0x5ecb, 0x1a } },
+	{ 0x46a40e74, 0x01, 0x00, 0x32, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x0c350, 0x28, 0, 0x20, 1, 1, 0x400, 0x20c, 0xffff, 0x27, 0x3364, 0x21 } },
+	{ 0x46a40ea4, 0x01, 0x00, 0x32, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x0ea60, 0x30, 0, 0x26, 1, 1, 0x400, 0x28f, 0xffff, 0x2f, 0x0e30, 0x27 } },
+	{ 0x46a40ed8, 0x01, 0x00, 0x32, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x11170, 0x38, 0, 0x2c, 1, 1, 0x400, 0x312, 0xffff, 0x36, 0xe2c9, 0x2e } },
+	{ 0x46a40f3c, 0x01, 0x00, 0x32, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x13880, 0x20, 0, 0x1e, 2, 1, 0x400, 0x083, 0xffff, 0x1f, 0x5ecb, 0x1a } },
+	{ 0x46a40f6c, 0x01, 0x00, 0x32, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x15f90, 0x24, 0, 0x1e, 2, 1, 0x400, 0x189, 0xffff, 0x23, 0x4c31, 0x1d } },
+	{ 0x46a40fa0, 0x01, 0x00, 0x32, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x186a0, 0x28, 0, 0x20, 2, 1, 0x400, 0x20c, 0xffff, 0x27, 0x3364, 0x21 } }
+};
+
+static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
+	0x46a40e10, 0, 0x7530, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f, 0x00, 0x00};
+
+#endif
+
 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
 {
 	int result = 0;
@@ -135,7 +157,7 @@
 			return -1);
 
 	/*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
-	vr_config = 0x01000500; /* Real value:0x50001 */
+	vr_config = PP_HOST_TO_SMC_UL(0x50001);
 
 	vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
 
